Unmanned Systems Technology 038 l Skyeton Raybird-3 l Data storage l Sea-Kit X-Class USV l USVs insight l Spectronik PEM fuel cells l Blue White Robotics UVIO l Antennas l AUVSI Xponential Virtual 2021 report

36 Focus | Data storage to program though, much longer than the nanoseconds of DRAM or SRAM, and it also needs a controller to manage how the data is stored and retrieved. The controller allows different algorithms for programming NAND chips and monitoring their health. Wear is also a major issue. Reading and writing a flash cell degrades the silicon each time, and using only one set of cells all the time would lead to a failure quite quickly. Instead, data is spread around the chip to avoid excessive wear on the cells, and some blocks of memory – around 10% of the memory chip – is held back, or partitioned, to be used to compensate if some cells fail for whatever reason. As the density increases, so the cells are smaller in size and so hold fewer electrons, which have to be split across multiple levels. That means the effects of wear or temperature are more significant with more levels and higher-density chips. A temperature sensor can be added into the controller to provide more information on what is happening with the memory, and compensate accordingly. Temperature variations can lead to a higher bit error rate and limit the memory’s lifetime. When these sensors are soldered onto a printed circuit board to avoid issues of vibration and shock then the overall lifetime is a more important design factor, especially with solid-state drives that are required to operate from -40 to +85 C and even up to 125 C. Having a separate controller allows the algorithms to check and refresh user data and system-level data on the chips. This includes ‘garbage collection’ to ensure that cells are properly erased and that stray charge does not create an error. Auto-calibration algorithms also check that each cell is performing as expected. Another support tool is error correction with parity checking. This uses an additional parity bit that travels with the data on a wider data path, with an SRAM buffer memory protected using cyclic redundancy checking. It provides additional parity for correction to recognise errors and avoid processing incorrect data. That is not sufficient for unmanned systems though, as there can still be cell failures where complete areas of the NAND array are destroyed. Compensating for this requires additional algorithms to check the cells. Another key utility is predictive maintenance. This requires more detailed data on the bit error rates and bit failures to determine where errors are occurring, for example in certain areas of the memory array. Identifying and avoiding these areas for storing data can boost the reliability and lifetime of the memory subsystem. Such a lifetime tool in the firmware of the controller can predict the expected lifetime but it needs to be designed for a particular capacity of drive and use data from testing and qualification. These background operations are the key to reliable long-term storage, with a typical minimum service life of 7 years. Having the controller provide a consistent interface to the data storage system is key for long-term usage. While the storage density of chips doubles every 18 months, there is a fundamental change in the underlying memory technology roughly every 5 years. Solid-state drive manufacturers June/July 2021 | Unmanned Systems Technology Charge distribution for multi-level NAND cells (Courtesy of SwissBit) Wear is a major issue. Reading and writing a flash cell degrades the silicon, and using only one set of cells would lead to failure quite soon